Smit Arekar. I design chips, from RTL to layout.

See the work Email me
Routed layout of the APB UART on SkyWater 130nm, plotted from its GDS: rows of standard cells, gold metal-2 wiring and pins along every edge.
My APB UART, plotted straight from its GDS. OpenLane on SkyWater 130nm: 530 synthesized cells, 1,767 placed with fill, on a 127 × 138 µm die.

Nine blocks. One chip.

That UART is one of them. Each block on this floorplan is a project: the RTL, the testbench, the layout, or all three. Scroll and the camera moves to it, or click a block.

A RISC-V core, plus an instruction of my own

A single-cycle RV32I core in Verilog, with a custom multiply-accumulate added in the custom-0 opcode space. Dot products are most of inference math, and MACC does each step in one instruction instead of two.

ISA
RV32I plus MACC: rd = rd + rs1 × rs2 in one cycle
Checks
8 self-checking testbenches and a golden cross-check, all passing
Reference
A Python ISA model written from the spec, not from the RTL
riscv-core
Datapath of the single-cycle RV32I core: PC, instruction memory, decoder, register file, ALU and the MACC unit.
Datapath, from the riscv-core README.

The hard part

A processor can be nearly right for a long time. A core with a broken sign-extension path still runs most programs, and one that mis-decodes a rare immediate format passes every test that never uses it. So every module has its own self-checking testbench, the full core runs six hand-assembled programs, and MACC results are cross-checked against an independent Python model of the ISA.

MACC also needed a third register read. rd is both the accumulator and the destination, and a standard register file only has two read ports.

What testing caught

The bug wasn't in the RTL. My assembler encoded the halt pseudo-op, jal x0, 0, as an absolute address instead of a relative offset, so halt jumped back to address 0 and reran the program. Every existing test passed by luck, because a deterministic program recomputes the same values. The golden model expected a true self-loop, never saw one, and flagged it. That's the case for a second implementation in one example.

At a glance

ISA
RV32I without FENCE, ECALL or CSRs, plus custom-0 MACC
Integration
6 hand-assembled programs, 7 core-level checks
Toolchain
Icarus Verilog, Python
Before this
A 32-bit 5-stage pipelined MIPS in Verilog with forwarding and hazard detection: RAW hazards resolved in under 3 cycles, 100% instruction coverage in simulation

smitarekar/riscv-core

GPU compute, from both ends

In RTL, a soft GPU with a SIMT architecture that I'm building in Verilog. On real silicon, matrix multiply kernels tuned on an Apple M4 GPU, because the quickest way to understand a GPU is to watch it waste its own throughput.

Peak
435.78 GFLOPS, coalesced kernel at 1024 × 1024
Tiling
1.88× faster than the naive kernel
Correctness
45 of 45 kernel and shape combinations match NumPy
metal-matmul
Memory hierarchy diagram showing how the naive, tiled and coalesced kernels move data between device memory, threadgroup memory and registers.
Naive to tiled to coalesced, from the metal-matmul README.

The hard part

A GPU gives you enormous throughput and almost no help using it. A kernel can run at a tenth of its capability and report no error, because nothing went wrong: the answer is right, it just took ten times longer. The arithmetic is identical in all three kernels here. What changes is how data moves between memory tiers.

Each kernel is checked against NumPy before a benchmark is allowed to run. Coalescing on top of tiling bought another 2.6% at 1024, which is inside run-to-run noise, and the README says so.

Why Metal

It was scoped as CUDA. My machine has no NVIDIA GPU, so the kernels are Metal. The memory-tier ideas carry over unchanged.

The SIMT GPU, in progress

The RTL side, built in four steps: a single-cycle scalar datapath, SIMT lane replication, branch divergence handled with active masks, and a tiled matrix multiply kernel to run on it.

smitarekar/metal-matmul

A systolic array that reads handwriting

A 4 × 4 weight-stationary systolic array in Verilog, then real MNIST digits run through it. The hardware's output matches the software reference bit for bit.

Accuracy
298 of 300 sampled MNIST images, 99.3%
Bit-exact
300 of 300 against the software reference
Latency
11 cycles: 4 to load weights, 7 to fill and drain
systolic-mm-accelerator
Data flow through the 4 by 4 array: activations stream west to east, partial sums accumulate north to south.
Data flow through the array, from the systolic-mm-accelerator README.

Sixteen processing elements each hold one weight and do one multiply-add. Activations stream west to east while partial sums accumulate north to south, in Q8.8 fixed point, over AXI4-Stream.

The hard part

A systolic array is a machine built out of timing. None of the PEs knows anything about the matrix being computed, so correctness comes entirely from data arriving at the right PE on the right cycle. The failure to fear isn't a wrong multiply. It's a value arriving one cycle early.

Running a real network

A small CNN trained in PyTorch, with its final classifier layer quantized to the array's exact Q8.8 format and mapped onto the hardware as three 4 × 4 weight tiles. Quantization changed none of the model's decisions, and the float model scores 98.5% on the full 10,000-image test set.

At a glance

Format
Q8.8 fixed point, 16-bit signed
Verification
54 directed checks, 3 cocotb suites over the real AXI4-Stream ports, 30 seeded random trials
Bugs found
2, both in test code rather than the RTL

smitarekar/systolic-mm-accelerator smitarekar/systolic-mnist-inference

An AXI4-Lite crossbar, verified two ways

Two masters, three slaves, a round-robin arbiter per slave per channel, and a defined DECERR for every unmapped address instead of a hang.

Checks
316 plain-Verilog checks across 6 testbenches
UVM
5 SystemVerilog UVM scenarios on Verilator with Accellera uvm-core
Bugs
3 in the RTL, and the two layers found different ones
axi4-crossbar
Crossbar topology: two masters, per-master address decode, one arbiter per slave per channel, three slaves.
Topology, from the axi4-crossbar README.

The hard part

An interconnect has no interesting arithmetic. Every bug in it is a timing or ownership bug, and they all fail the same way: a transaction that never completes, on a bus where nothing times out.

What testing caught

Same-cycle completion. A fresh grant, AW and W can all resolve on one clock edge. The first arbiter's FSM only read its pre-edge state, so it couldn't see a completion its own forwarding had just caused, and the transaction looked like it hung forever. The plain-Verilog suite found that one; UVM found others.

Measured, not assumed

The back-to-back gap between two uncontested writes is measured in simulation, 20 ns, rather than asserted from a number typed by hand.

smitarekar/axi4-crossbar

PCIe, the two layers above the wire

The transaction layer and data link layer of a PCIe Gen1/Gen2 endpoint in Verilog, ending in a real two-endpoint loopback. No PHY yet; the data link layer exposes a byte stream for one.

Checks
62,963 passing, 0 failing, lint clean
RTL
21 modules, 15 self-checking testbenches
Models
6 independent Python golden models
pcie-tl-dl
Module hierarchy of the PCIe endpoint top: transaction layer, flow control, configuration space, and data link layer.
Module hierarchy, from the pcie-tl-dl README.

The hard part

PCIe is a spec most people implement from memory of a diagram, and that's where the bugs come from. CRC seeds, bit orderings, and header bits that routing elements may legally rewrite are all easy to assume by analogy and wrong to assume without checking.

What's still open

All six build phases are done. Two details, the LCRC wire byte order and the DLLP CRC-16 polynomial, are self-consistent for this design's own loopback but not yet checked against the PCI-SIG spec text, and five open items are listed in the README for sign-off.

smitarekar/pcie-tl-dl

One UART, from RTL to GDSII

An APB UART taken through the whole flow in three repos: the RTL, a UVM environment for it, and a physical design on SkyWater 130nm that came out DRC and LVS clean on the first pass.

Signoff
0 DRC violations, LVS clean across 663 nets
Timing
1.2 ns critical path against a 20 ns period
UVM
cocotb and pyuvm, 5 of 5 tests, 9 of 9 coverage bins
uart-asic-flow
Routed layout of the APB UART on Sky130, plotted from its GDS: rows of standard cells under metal routing, with pins along every edge.
The routed layout, plotted from the uart-asic-flow GDS.

The RTL

A baud generator, a transmitter, a 16× oversampled receiver with glitch-checked start-bit detection, and four memory-mapped registers, so a CPU on an APB bus can send and receive serial bytes. 4 of 4 testbenches, 29 checks.

The verification

A real UVM component hierarchy without a commercial simulator: cocotb and pyuvm on Icarus Verilog. The scoreboard checks against an independently decoded serial stream, because a loopback can't tell you a byte is right when both halves of the trip run through the same design. The DUT is a pinned git submodule, so testbench and design version independently.

What testing caught

My own driver. It signalled done as soon as the TXDATA write finished instead of when the byte finished shifting out, so the baud-sweep test changed BAUDDIV mid-frame, which the DUT's README says never to do. The monitor decoded the first two or three bits of a frame correctly and then drifted into garbage.

The layout

OpenLane on Sky130 HD: synthesis, floorplan, placement, clock tree, routing and signoff in one pass. 530 cells synthesized, 1,767 placed with fill, 0.0176 mm² of die at 42.6% utilization. The one finding was five max-fanout guideline violations on clock buffers, and timing still closed.

smitarekar/apb-uart smitarekar/apb-uart-verification smitarekar/uart-asic-flow

512 bits of SRAM, drawn by hand

A 512-bit 6T SRAM in 45nm, taken from RTL through schematic to full-custom layout in Cadence Virtuoso, with the sense amplifiers, decoder and precharge built around four 128-bit banks.

Read latency
18% lower after Logical Effort sizing
Active power
22% lower
Extraction
Quantus parasitic extraction on the final layout

This one was coursework, so there's no public repo. The die drawing shows it the way it was built: four banks of 128 bitcells, with the decoder down the middle and the sense amplifiers and precharge along the shared edge.

At a glance

Process
45nm, Cadence Virtuoso
Array
512 bits as 4 × 128-bit banks of 6T cells
Periphery
Sense amplifiers, row decoder, precharge
Flow
RTL, schematic, full-custom layout, Quantus extraction
Result
Read latency down 18%, active power down 22% with Logical Effort sizing

Analog, one transistor at a time

Four circuits designed at the transistor level in Cadence Virtuoso, all targeting tape-out in TSMC 16nm FinFET. The digital blocks on this die end at a standard cell. These start below it.

Amplifiers
Differential TIA, complementary C2iAmp
Oscillator
Ring VCO, RC and L cross-coupled
Switched-cap
Fully differential switched-capacitor op amp

Coursework, so there's no public repo. All four circuits were designed and simulated at the transistor level in Cadence Virtuoso and Spectre, targeting a TSMC 16nm FinFET tape-out.

At a glance

Process
TSMC 16nm FinFET
Tools
Cadence Virtuoso, Spectre
Circuits
Differential TIA, complementary C2iAmp, ring VCO (RC and L cross-coupled), fully differential switched-capacitor op amp

A Kalman filter, from Python to fixed-point RTL

An Extended Kalman Filter that tracks a 2D target from noisy range-bearing radar measurements. Written first in float64 Python, then ported to fixed-point Verilog and checked against the Python at every step, not just the last.

Error
6.462 m RMSE in fixed point against 5.947 m in float64
Format
Q11.14 datapath, Q15.14 for S, det(S) and its inverse
Match
60 of 60 steps within tolerance, CORDIC for the trig
ekf-target-tracker
EKF predict and update datapath: state prediction, covariance update, innovation, CORDIC and gain computation.
Predict and update datapath, from the ekf-target-tracker README.

The hard part

A Kalman filter is a feedback loop over a covariance matrix. A small rounding error in P this step becomes a slightly wrong gain next step, which makes a slightly wrong state, which makes a worse P. In floating point that loop is stable. In fixed point it isn't guaranteed to be.

Range noise and bearing noise here live about 5.7 orders of magnitude apart, so the inverse of S legitimately reaches about 9,133. Q11.14 tops out at ±2,048, which is why S gets a wider format than the rest of the datapath.

Where I've used it before

The Borosil data logger ran an EKF in its DSP pipeline to hold ±0.03 °C RTD accuracy. This project does the same math with the floats taken away.

smitarekar/ekf-target-tracker

Hardware that shipped.

Two years at Borosil Scientific in Pune turning FPGA designs into lab instruments, including one I invented and patented. Before that, an internship on a defense DSP pipeline.

Borosil Scientific

Product Lead Jul 2024 to Jun 2025

Rotary evaporator

±0.1°CBath stability, 27 to 200 °C

Led an 18-month R&D program and architected an FPGA DSP-PID closed loop on a Zynq SoC. Bath stability of ±0.1 °C from 27 to 200 °C, and 35% better process repeatability.

Data logger

±0.03°CRTD accuracy

Led the RTL lifecycle of an 8-channel Zynq FPGA logger with AXI4 integration, from RTL through timing closure to board bring-up. Its EKF DSP pipeline holds RTD accuracy to ±0.03 °C.

Kjeldahl nitrogen analyzer

7minPer sample, from 20

Led the KDI R&D. FPGA signal acquisition with under 0.1% nitrogen measurement error (AOAC 976.05), and firmware automation that took per-sample analysis from 20 minutes to 7.

3DExperience PLM

−43%NPI cycle time

Led the rollout across three business units and 500+ hardware, software and mechanical engineers. BOM governance and digital-twin workflows cut NPI cycle time 43% and BOM revision errors 36%.

Borosil Scientific

Design Engineer Jul 2023 to Jun 2024

ARD, patented

+28%Distillate purity

Invented the ARD, a system for separating azeotropic mixtures. FPGA solenoid-valve actuation and DSP flow monitoring raised distillate purity 28% and cut operator setup time 45%. Indian Patent 202321080252, with Sreejith Kumar and Rohit Walvekar.

Precision lab instruments

0.001AbsUV spectrometer

AXI4 SoC control firmware for a water bath (±0.05 °C, ISO 3696), a UV spectrometer (0.001 Abs, under 0.5 nm, 190 to 1100 nm) and ADB dispensers (ISO 8655, under 0.5% CV).

Automatic fiber analyzer

−60%Operator intervention

UVM-verified FPGA supervisory control and safety-interlock firmware that automated three-stage acid and alkali digestion, with 60% less operator intervention than the manual baseline.

BitMapper Integration Technologies

Design Engineer Intern Nov 2021 to Feb 2022

Guidance DSP pipeline

<2µsReal-time latency

An RTL DSP pipeline in VHDL and Verilog for a classified DRDO missile guidance and homing system, meeting under 2 µs real-time latency. Wrote the test procedures for a two-FPGA common processing board with 27 input channels.

Zynq SOM bring-up

4axesMotor driver

Embedded firmware and hardware bring-up for a Zynq-7000 SOM (ARM Cortex-A9 plus FPGA) and a daughterboard with a 4-axis motor driver, built for India's defense tri-services.

Hi, I'm Smit.

I like the part of hardware where a design has to survive contact with something that doesn't care what I meant: a testbench, a timing report, a DRC deck. I spent two years at Borosil Scientific turning FPGA designs into lab instruments, then came to USC to go deeper into the parts of a chip I want to build next: CPUs, GPUs and the accelerators around them.

NowMS, Electrical Engineering, University of Southern CaliforniaBuilding the nine blocks in Work

Engineering from the transistor up.

Every layer I've worked at, from FinFET devices to instruments on a lab bench, with the tools I used there and the work that proves it.

  1. Devices

    TSMC 16nm FinFET, Cadence Virtuoso and Spectre

  2. Custom layout

    Cadence Virtuoso on 45nm, Quantus extraction, DRC and LVS

  3. Physical design

    OpenLane on SkyWater 130nm, static timing analysis, DRC and LVS

  4. RTL

    Verilog, SystemVerilog, VHDL, Assembly

    Earlier: a 32-bit 5-stage pipelined MIPS in Verilog, whose forwarding and hazard detection resolve RAW hazards in under 3 cycles with 100% instruction coverage in simulation. And a single-clock FIFO, 16 deep and 5 bits wide, built with both n-bit and (n+1)-bit pointers plus almost-full and almost-empty flags.

  5. Verification

    UVM, cocotb, pyuvm, QuestaSim, ModelSim, Verdi, Icarus Verilog, Verilator

  6. FPGA and SoC

    Xilinx Zynq and Vivado, AXI4 IP integration, CDC analysis, PetaLinux and Yocto, RTOS, DSP, PID control, MATLAB

  7. Software on accelerators

    C, C++, Python, CUDA, Apple Metal, PyTorch, OpenCV

  8. Boards and instruments

    Altium, Ansys HFSS, 3DExperience PLM

    Earlier: a dual-band S and C-band microstrip patch antenna for an ISRO StudentSat, tuned in Ansys HFSS for resonance and radiation pattern.

Off the clock

Motorcycles, photography and dark skies. A good weekend ends somewhere like Joshua Tree, with a camera on a tripod pointed at the Milky Way.

Let's talk silicon.

Email is the fastest way to reach me.

arekar@usc.edu